The present invention relates to a semiconductor device, which can be used appropriately as, e.g., a semiconductor device including two circuits to which different power supply potentials are supplied.
In a semiconductor device provided with a control circuit which generates a control signal for a power semiconductor element, between the control circuit (first control circuit) and the power semiconductor element, another control circuit (second control circuit) is provided to input the control signal to the power semiconductor element. A power supply potential to the second control circuit is generally equal to or lower than a power supply potential to the power semiconductor element and higher than a power supply potential to the first control circuit. The control circuit supplied with the lower power supply potential and the control circuit supplied with the higher power supply potential are electrically isolated from each other by an isolation region using a pn junction.
Between the control circuit supplied with the lower power supply potential and the control circuit supplied with the higher power supply potential, a level shift circuit for shifting a voltage level is provided to transmit the control signal. The level shift circuit has a level shifter made of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as a coupling transistor which couples the control circuit supplied with the lower power supply potential to the control circuit supplied with the higher power supply potential.
Specifically, to transmit the signal from the control circuit supplied with the lower power supply potential to the control circuit supplied with the higher power supply potential, the level shift circuit has a level-up shifter made of an re-channel MOSFET as a coupling transistor. Conversely, to transmit the signal from the control circuit supplied with the higher power supply potential to the control circuit supplied with the lower power supply potential, the level shift circuit has a level-down shifter made of a p-channel MOSFET as a coupling transistor.
Japanese Unexamined Patent Publication No. Hei 9(1997)-283716 (Patent Document 1) discloses a technique in which, in a semiconductor device, a slit-like region having a first conductivity type is interposed between a second region having a second conductivity type and a third region having the second conductivity type and a pn junction formed of the second or third region and the slit-like region is depleted.
Japanese Unexamined Patent Publication No. 2005-123512 (Patent Document 2) discloses a technique in which an NMOS is used for a level shift from a lower-potential reference circuit region to a higher-potential reference circuit region and a PMOS is used for a level shift from the higher-potential reference circuit region to the lower-potential reference circuit region